VLSI
LAB
Digital VLSI Design
BTEEV602 · Dr. Sohel Rana · SCET
Question Bank + MCQ Test
Shreeyash College of Engineering & Technology

Chapter-wise Question Bank
& Randomized MCQ Test

5 Long Questions · 5 Short Questions · 10 MCQs per chapter — plus a randomized 50-question practice test with timer

5 Units
25 Long Q&A
25 Short Q&A
50 MCQs (practice)
50 MCQs (random test)
UNIT I
Introduction to VLSI Design
Moore's Law · VLSI Design Flow · Y-Chart · Design Styles · Physical Design · Stick Diagrams · Euler's Rule
LONG Q&A5 Long Answer Questions
SHORT Q&A5 Short Answer Questions
MCQ PRACTICE10 Multiple Choice Questions
UNIT II
Traditional MOS Design
Pseudo-NMOS Logic · Inverter Analysis · Threshold Voltages · Transient Response · CMOS Inverter Logic
LONG Q&A5 Long Answer Questions
SHORT Q&A5 Short Answer Questions
MCQ PRACTICE10 Multiple Choice Questions
UNIT III
Combinational MOS Logic Circuits
NMOS Loads · CMOS NOR & NAND · Boolean Realization · AOI/OAI Gates · CMOS Full Adder · Ratioed Logic
LONG Q&A5 Long Answer Questions
SHORT Q&A5 Short Answer Questions
MCQ PRACTICE10 Multiple Choice Questions
UNIT IV
Sequential MOS & Transmission Gate Circuits
Bistable Elements · SR Latch · Clocked D Latch · Edge-triggered Flip-Flop · TG Multiplexer · XOR · TG Registers
LONG Q&A5 Long Answer Questions
SHORT Q&A5 Short Answer Questions
MCQ PRACTICE10 Multiple Choice Questions
UNIT V
Dynamic CMOS Circuits
Precharge/Evaluate Logic · Domino Logic · Charge Sharing · NORA Logic · Zipper CMOS · High-Speed Cascades
LONG Q&A5 Long Answer Questions
SHORT Q&A5 Short Answer Questions
MCQ PRACTICE10 Multiple Choice Questions

⚡ Randomized MCQ Test

50 questions — 10 randomly selected from each of the 5 units. Each attempt is unique!

Questions: 50
Duration: 50 min
Per Correct: +1 Mark
Negative Marking: None